Semiconductor memory devices have been continuously developed to improve the operation speed thereof with increase of their integration density. For example, synchronous memory devices operating in synchronization with clock signals have been revealed to improve the operation speed thereof.
Single data rate (SDR) synchronous memory devices have been first proposed to enhance the operation speed of the semiconductor memory devices. The SDR synchronous memory devices receive or output the data in synchronization with every rising edge of an external clock signal. However, high performance memory devices, which are faster than the SDR synchronous memory devices, are still required to meet the requirements of high performance electronic systems. Accordingly, double data rate (DDR) synchronous memory devices operating at a higher speed than the SDR synchronous memory devices have been proposed recently. The DDR synchronous memory devices may receive or output the data twice during a single period of an external clock signal. That is, the DDR synchronous memory devices may receive or output the data in synchronization with every rising edge and every falling edge of the external clock signal. Thus, the DDR synchronous memory devices may operate at a speed which is twice as higher than that of the SDR synchronous memory devices even without an increase in the frequency of an external clock signal.
Meanwhile, the DDR synchronous memory devices use a multi-bit pre-fetch scheme that internally processes multi-bit data at a single time. According to the multi-bit pre-fetch scheme, multi-bit data serially inputted may be arranged in parallel in synchronization with a data strobe signal, and the multi-bit data arranged in parallel may be simultaneously stored in memory cells by a write command signal. Specifically, the multi-bit data arranged in parallel may be transmitted to a write driver by a data input clock signal and the data transmitted to the write driver may be finally stored into the memory cells through global lines at a single time by an enable signal.